Multi-Cycle RISC-V CPU in Verilog

What it is

A multi-cycle RISC-V CPU written in Verilog for EPFL's Computer Architecture course. It runs RISC-V assembly, handles interrupts and drives a board's peripherals through memory-mapped I/O.

What I built

I built the whole CPU on my own. The datapath has the ALU, register file, instruction register, multiplexers, and shift and logic units. Around it sit an FSM-based control unit, RAM, and control and status registers (CSRs) with interrupt support.

Through memory-mapped I/O the CPU drives LEDs, buttons, a joystick, DIP switches, seven-segment displays and an LCD. I wrote RISC-V assembly that runs on it to exercise interrupt-driven I/O against those peripherals, and tested the design with a Verilator testbench.

The interesting problem

Debugging the control logic was hard. The control unit is a state machine that walks each instruction through its cycles and sets the control signals at every step.

I tested it one piece at a time in Verilator, with separate testbenches for its next-state logic, ALU operation, immediates and outputs.